For students
Pick a brief below, or bring the problem statement your department handed you. We architect it with you, review every commit, deploy it to a real URL, and rehearse the viva until no question surprises you.
See student support5 scoped briefs
3 mini · 2 major
Hardware is not software with a different syntax: the compiler is a synthesis tool, the debugger is a waveform, and the only report that counts is timing, area and power. Student VLSI projects fail the same three ways — RTL that simulates but never synthesises, a testbench that only feeds the cases the designer already thought of, and a claim of correctness with no coverage number behind it — so we build in the opposite order: a self-checking testbench and a coverage goal first, then RTL that closes timing on a board or inside a real PDK. Two of these briefs need an FPGA board (a Basys 3 for the UART, a Nexys A7 for the RISC-V core); the multiplier, the FIFO verification environment and the Sky130 ASIC flow need nothing but a laptop, and every tool here is free — open source, or Vivado's free edition.
Two audiences, one engineering standard
Pick a brief below, or bring the problem statement your department handed you. We architect it with you, review every commit, deploy it to a real URL, and rehearse the viva until no question surprises you.
See student supportRTL design and verification support: cocotb and UVM-style testbenches taken to coverage closure, FPGA prototyping, and blocks pushed through synthesis to timing, area and power sign-off on an open PDK.
Discuss a company buildMini projects
Three to four weeks. Narrow enough to finish, deep enough that you learn the decision that actually matters.
A synthesisable UART with 16x oversampling and a cocotb bench that checks itself against a golden model — covering the framing, parity and ±2% baud-drift cases a loopback demo quietly hides. The same bench is then re-run on the Yosys netlist, where inferred latches and X-propagation surface.
You walk away with
A radix-4 Booth-encoded, Wallace-tree 16x16 multiplier pipelined until it meets a target clock, then benchmarked against the one line of Verilog that would have let Vivado infer a DSP48 slice for free. The comparison is the lesson.
You walk away with
A small iterative AES-128 core taken from RTL to a DRC-clean and LVS-clean GDS-II on the Sky130 PDK with LibreLane — no tapeout at the end, just the layout and the reports. The RTL is deliberately small so the weeks go into the flow: floorplan, utilisation, timing closure, and a power number honest about the switching activity behind it.
You walk away with
Major projects
Ten to twelve weeks. Architecture, trade-offs, failure modes, deployment, and evidence—the project that carries an interview.
A 5-stage RISC-V core with full forwarding, load-use stalling and branch flushing, running a GCC-compiled C program on a Nexys A7. The datapath is the easy half: the hazard logic, and the machine-mode CSRs and trap path that riscv-tests silently depends on, are the project.
You walk away with
A PyUVM constrained-random environment for a dual-clock FIFO, taken to a stated functional coverage target and then attacked with injected bugs to prove it catches defects instead of just running green. Verilator is 2-state and zero-delay, so it cannot see metastability: the CDC evidence is a formal proof of the Gray-code pointer protocol, not the simulation, and the brief says so.
You walk away with
Explore more
Bring us a product brief, a business problem, or a final-year project. We’ll turn it into a clear scope, a working build, and a handover you fully own.
Prefer email? info@tenzok.in